In recent years, with advancement of mobile devices and the like, semiconductor memory devices requiring low power consumption have been demanded. Against such a background, various types of semiconductor memory devices have been developed, a typical example of which is Dynamic Random Access Memories (DRAMs). In addition, these DRAMs are classified into one of the following standards, namely, a normal standard (DDR3) in which the power supply voltage is 1.5 V, a low voltage standard (DDR3L) in which the power supply voltage is 1.35 V, and an ultra-low voltage standard (DDR3U) in which the power supply voltage is 1.25 V. When manufacturing these three types of semiconductor memory devices having different power supply voltages, it is more advantageous in terms of cost to design and manufacture the semiconductor memory devices as a single chip and sort the semiconductor memory devices into the respective standards in a sorting process, rather than to design and manufacture the semiconductor memory devices as different chips. More specifically, it is only necessary to select chips satisfying the low voltage standard and chips satisfying the ultra-low voltage standard from a plurality of chips designed and manufactured as the normal voltage standard products.
In addition, in recent years, a very high data transfer rate has been required for data transfer of semiconductor memory devices (between a CPU and a memory). To realize this, the amplitude of input/output signals has been increasingly reduced. If input/output signals have a smaller amplitude, the accuracy required for the impedance of an output buffer is significantly increased. To address such requirement, normally, an output buffer having an impedance adjustment function is used. Normally, the impedance of an output buffer is adjusted by using a calibration circuit.
Japanese Patent Kokai Publication No. 2000-49583A (Patent Literature 1) discloses an output circuit capable of adjusting the output impedance thereof. The output circuit includes a plurality of transistors connected in parallel to each other, and each transistor is controlled by an impedance adjustment clock signal ZSCK (see FIG. 2 in PTL 1).
Japanese Patent Kokai Publication No. 2010-166299A (Patent Literature 2) discloses an impedance adjustment circuit that performs impedance adjustment by controlling on/off of each of a plurality of transistors that are connected in parallel to each other and that are included in an output buffer. The impedance adjustment circuit uses a replica buffer having substantially the same configuration as that of the output buffer (see FIG. 1 in Patent Literature 2).
Japanese Patent Kokai Publication No. 2006-203405A is listed as Patent Literature 3.